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Improve Performance And Reduce Cost

By carefully matching the VRM, PCB planes, and load circuits to each other and to the required impedance magnitude, a flat PDN impedance can be created while minimizing circuit board area. The optimization also minimizes the use of expensive low-ESR capacitors and low-impedance voltage regulators.

Engineers are under constant pressure to improve the performance of their products while reducing product cost. The key to doing so is a better understanding of the power distribution network (PDN) noise path.

The minimum noise is achieved when a source, interconnect, and load are all well matched, as exemplified in many test and measurement instruments. Signal generators, oscilloscopes, spectrum analyzers, and vector network analyzers are often 50 ohm, connected using 50-ohm coaxial cables through 50-ohm connectors.

There are other standard impedance levels, such as the 100 ohm often used in digital pathways and 75 ohm used in CCTV. Yet all of these instruments use the matched interconnect system to maximize performance while minimizing noise. This also applies to PDNs.

Breaking It Down

A PDN consists of a voltage regulator (VRM) and interconnecting printed-circuit board (PCB) planes, traces, and loads, which are the circuits being powered. Figure 1 illustrates the impedance of a well balanced PDN. This PDN has an arbitrary impedance of 3.3 ohm. The VRM output impedance (RVRM) is 3.3 ohm, the PCB plane impedance (ZPCB) is 3.3 ohm, and the load circuit impedance (RLOAD) is 3.3 ohm, resulting in an ideal, perfectly flat PDN as seen in the red trace.

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