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PRODUCTS WE WILL BE EXHIBITING AT DESIGNCON 2024

At DesignCon 2024 we will be exhibiting the following products in our booth;

 

  • High-Speed Transient Load Steppers for ASIC, Data Center, AI, and other high-power applications

  • Our new High-Power Line Injector

  • New capabilities in VNA Component Testing and Modeling

  • Power Integrity Testing

  • PDN Impedance / VRM Stability

  • Noise Immunity Testing

 

Other companies exhibiting at the show will also have Picotest products - find our set-ups at

Tektronix, Siglent, Rohde & Schwarz, and PacketMicro.

DESIGN, SIMULATION & VALIDATION CHALLENGES OF A SCALABLE 2000-Amp CORE POWER RAIL

Wednesday, January 31st • 9:00 AM - 9:45 AM PST

Locations: Ballroom C

Are you looking for a new way to address power supply noise immunity concerns in high-performance transceiver testing? New water-cooled probe-based testing solution for high-speed signal integrity noise injection is presented. Testing of PSRR, PSMR, and PSNR applications are explored.

Featuring Picotest's P2124A - the world's first water-cooled probe!

Speakers: Steve Sandler, Managing Director at Picotest, Benjamin Dannan, Chief Technologist at Signal Edge Solutions, Heidi Barnes, Applications Engineer for PI & SI at Keysight Technologies, Idan Ben Ezra, Senior Hardware & PI Engineer at Broadcom Semiconductors, Yu Ni, Supervisor, Module Design Engineering at Monolithic Power Systems

Description:

This paper will demonstrate how to measure, model, and validate a scalable, 2k-Amp core power rail. The technological growth in Data Centers, AI, Graphics, and Super-Computing has pushed the core power rail current to 2k-Amps and is climbing. Designing such a power rail is a complex task, involving architectural design choices as well as simulation and validation challenges. Lower core voltages reduce power but also reduce operating noise margins. Combined, these require greater expertise in design choices, much greater simulation accuracy, and more rigorous validation of the power rail. This paper will address this 2k-Amp project from the beginning with a variety of architectural design choices and resulting modeling and simulation challenges, including cascaded VRMs, current sharing, and thermal simulation. The assessment of PDN impedance has become a well-published mantra, and yet core power rail validation generally requires time domain testing as well as impedance testing, which presents yet greater challenges. Therefore, the final validation of this design is done using time domain testing at full ASIC power with dynamic modulation at package speeds of up to 100MHz to address the large signal response phenomenon. Simulation to measurement correlation will be shown for electrical and thermal behavior.

 

Takeaways:

Live demonstrations of PSRR testing of power supplies using an MSO6 oscilloscope, PSMR using Signal View software, and PSNR using a 112Gb/s PAM-4 – PCIe application will be presented.

 

Intended Audience:

• Basic knowledge of GaN design and thermal concerns in high-performance interconnect testing
• Power Supply testing and noise impacts on Signal Integrity concerns

• Basic understanding of transceiver test evaluation and analysis
• Basic knowledge of power supply noise performance testing including rejection ratio, noise rejection, and modulation ratio
• Basic concepts of PCIe, PAM-4 and 400G/800G

HANDS-ON PDN IMPEDANCE & CALIBRATION BASICS

Wednesday, January 31st • 1:15 PM - 2:00 PM PST 
Location: Chiphead Theater

You have probably heard of calibration, de-embedding, and fixture removal for network analyzer measurements, but do you know how to do it for a 2-port shunt low-impedance measurement? Impedance measurements are a must-have skill for Power Integrity engineers. The measurements provide models for Capacitors, Resistors, and Inductors that work in both time and frequency domain simulations. Impedance measurements are also critical for verifying the performance stability of a power delivery network (PDN). In this session, you'll learn the difference between these terms. You'll learn, with demonstrations, how to remove the impact of fixturing using calibration and de-embedding steps. The process works for both connectorized devices or with PCB browser probes to provide accurate measurements that are compatible with your PCB EM simulator.

Speakers: Steve Sandler, Managing Director at Picotest, Benjamin Dannan, Chief Technologist at Signal Edge Solutions, Heidi Barnes, Applications Engineer for PI & SI at Keysight Technologies

 

Takeaways:

The audience will be presented with a new way to address power supply noise immunity concerns in high performance transceiver testing. New water-cooled probe based testing solution for high speed signal integrity noise injection is presented. Testing of PSRR, PSMR, and PSNR applications are explored.

 

Intended Audience:

• Basic knowledge of GaN design and thermal concerns in high performance interconnect testing
• Power Supply testing and noise impacts on Signal Integrity concerns
• Basic understanding of transceiver test evaluation and analysis
• Basic knowledge of power supply noise performance testing including rejection ratio, noise rejection, and modulation ratio
• Basic concepts of PCIe, PAM-4 and 400G/800G

PANEL DISCUSSION - THE IMPACT OF DATA CENTER & AI GROWTH ON SI/PI ENGINEERS

Wednesday, January 31st • 4:00 PM - 5:15 PM PST

Location: Ballroom B

Speakers: Steve Sandler, Managing Director at Picotest, Benjamin Dannan, Chief Technologist at Signal Edge Solutions, Chris Loberg, Sr. Technical Marketing Manager at Tektronix, Heidi Barnes, Applications Engineer for PI & SI at Keysight Technologies, Jason SekaninaµModule Business Dev’t & Product Apps at Analog Devices

Datacenter, AI, and other Super Computing applications are growing exponentially.  This has exerted pressure in a number of areas.  We are seeing power domains exceeding 2,000 Amps in socket.  This puts pressure on the semiconductor companies to manufacture even higher density and higher efficiency power modules.  We are showing examples of these new power modules in our DesignCon paper, titled "Design, Simulation & Validation Challenges of a Scalable 2000 Amp Core Power Rail."  There are numerous other implications as well.  Target impedance levels are at or below 30uOhms, which is a challenge to measure, requiring new instrument interfaces.  Large signal dynamic current transients are not evident from impedance measurements and are even more challenging.  These power levels also put a strain on thermal designs of both the chip and the board, requiring electro-thermal simulation.  The near fields from the 2000Amp switching pollutes the nearby SI lines requiring system-level analysis, including PI/SI crosstalk and EMI.  And measuring the di/dt of the dynamic current also presents new challenges.  Yet another issue is the increasing number of, and speed, and therefore higher power, transceivers.  These transceiver requirements are also straining available test methodologies and in particular thermal design.  These impacts are apparent in the updates to the QSFP transceiver specifications.

This distinguished panel was hand-selected to represent the engineers in the trenches.  They’ll each discuss how this exponential growth in high-power computing is affecting them, whether it is changes to workflow, the development of new processes and methodologies, the demand for instrument developments that include more detailed waveform analysis, or other implications.  It’s a great opportunity for the attendees to ask questions and learn about these impacts.  If they haven’t been subjected to these challenges, rest assured they will!!   

Takeaways:

The audience will be presented with a new way to address power supply noise immunity concerns in high-performance transceiver testing. New water-cooled probe-based testing solution for high-speed signal integrity noise injection is presented. Testing of PSRR, PSMR, and PSNR applications are explored.

Intended Audience:

• Basic knowledge of GaN design and thermal concerns in high-performance interconnect testing
• Power Supply testing and noise impacts on Signal Integrity concerns
• Basic understanding of transceiver test evaluation and analysis
• Basic knowledge of power supply noise performance testing including rejection ratio, noise rejection, and modulation ratio
• Basic concepts of PCIe, PAM-4 and 400G/800G

RELEVANT APPLICATION NOTES

VRM Modeling and Stability Analysis for the Power Integrity Engineer

Steve Sandler, Benjamin Dannan, Heidi Barnes, Christian Yots, SI Journal, January 06, 2024

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.

The Challenge of Measuring a 40 µΩ, 2000 Amp PDN With a 2-Port Probe: The Measurement Result

Steve Sandler, Benjamin Dannan, SI Journal, Jan 4th, 2024

Having determined the amount of CMRR needed for 2-port measurement in the previous installment of this blog, Steve Sandler and  Benjamin Dannan follow up return with a demonstration of how to create a DUT and make a 40 µΩ impedance measurement with the 2-port probe.

The Challenge of Measuring a 40 µΩ, 2000 Amp PDN With a 2-Port Probe: How Much CMRR is Needed?

Benjamin Dannan, Steve Sandler, SI Journal, Jan 6th 2024

In this blog, Steve Sandler and Benjamin Dannan demonstrate how to determine how much CMRR is needed when introducing a ground loop isolator to correct the error in a 2-port measurement. 

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FIND ME AT DESIGNCON

Look for Picotest and ask for a free probe measurement keychain board!

#DesignCon

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