Updated: Sep 12, 2020
Published on June 5, 2020 by Ken Coffman Field Applications Engineer at Vicor Corporation
Ken Coffman: Steve, first off, let’s discuss your latest book, Power Integrity using ADS. ADS is Keysight’s Advanced Design System. Literally, you could use any simulator you like. Can engineers who don’t use ADS get value from this book?
Steve Sandler: Certainly! The book provides simulation details for ADS and includes the ADS Workspaces, but the procedures and workflow apply to many other simulators as well. I know some engineers who use the capacitor modeling in SPICE. Many of the characteristics we show in the book are useful in any simulator, though we show the step-by-step guidance in ADS.
KLC: When a power supply’s load current changes, the VRM control loop detects and changes the output voltage to maintain regulation. This means the power supply is inherently inductive. One of the main challenges of a PDN design is managing this inductance—which you call excess inductance. In your experience with engineers chasing this excess inductance, what is the winning strategy? And, how does that compare with what you often see in power supply designs?
SMS: Great question. Yes, I published an article on this subject (see Reference 1). Our goal is generally to achieve flat impedance. This means that the inductors and capacitors have to balance each other out. Less excess inductance means less capacitance is required. I like to measure a few regulator options and generally pick the one with the lowest inductance. Power engineers often struggle with the difference between inductance and excess inductance. A coaxial cable is both inductive and capacitive. The characteristic impedance of the cable, usually 50 Ohms, means the square root of L/C is equal to 50 Ohms. Terminating the cable results in ZERO excess inductance, though the cable is still inductive. It’ s a bit of a brain twister.
KLC: I understand the hazard of too high of an output impedance—for a current change, the output voltage will change more than we want. I also understand the problem of high-Q, low-impedances at certain frequencies—for every resonance, there is a price paid with high-impedances at frequencies above resonance. What is the hazard if the impedance is too low (but flat)?
SMS: If the impedance is flat and too low, life is good. Mostly. It means that you spent more than you needed to on the PDN capacitors and voltage regulator. Ultimately, when you get to the BGA, you would optimally meet the characteristic impedance of the package. Here, an inductance that is too low increased the die noise. Heid Barnes (Keysight), showed that in our DesignCon 2020 paper with Jack Carrel (Xilinx) (see Reference 2).
KLC: You do a lot of work with linear regulators. To most of us engineers, this seems like the simplest thing we know. Generally, a linear regulator has three terminals and one is connected to ground? How hard can they be?
SMS: A switching regulator is essentially a state machine. Switches are ON or OFF, so it’s pretty easy to keep track of them and the design is somewhat switch independent. In an LDO the device operates in its linear region. This is continuously variable analog and heavily dependent on device operating points and small signal parameters. There are also a few different common topologies and we don’t generally know which topology the device is. Finally, I think the only reason engineers think these devices are simple because the manufacturers present them that way to avoid scaring them off.
KLC: I will ask about your viewpoint on GaN technology later, but do you see a role for GaN in the lowly linear regulator? What advantage will it bring to these devices?
SMS: I’ve given a few papers on this, but GaN will be everywhere—I’ve specifically given papers on GaN LDO’s. More bandwidth and higher transconductance means less excess inductance. Less excess inductance means less output capacitance. Also, smaller, cheaper, lower dropout voltages and lower noise. This all seems like a win-win-win-win-win to me.
KLC: You’ve been forthcoming about your historic experience with Power MOSFETs—how you initially dismissed them and thought they would be unsuccessful. With GaN transistors, it seems like you want to avoid that error. You are clearly on the GaN bandwagon. What do you see in GaN technology—advantages and disadvantages?
SMS: I bet against Alex Lidow [CEO of EPC, Efficient Power Conversion Corporation] once, I won’t do it again. Alex says GaN outperforms Si in EVERY characteristic. This is true. It takes work to find any disadvantage, but I’ll mention two. For the guy playing in his lab, its much harder to solder them yourself. I don’t solder them in. I ask EPC for help or I purchase pre-assembled boards and that works well. And, the devices are unbelievably fast—which is a huge design challenge. See Reference 3. EM simulation is highly recommended since these devices can oscillate well into the GHz just due to connection inductance.
KLC: This has been going on for a while and is partially driven by GaN speeds, but power supply design is changing into RF design. More and more, we’re using RF terminology and employing transmission line methods. This is a whole new world for many power engineers—and many ignore or resist the trend. Why is this happening? For the power engineer who wants to be relevant in the job market of the future, what is the smart strategy for managing these inevitable changes?
SMS: I hear this a lot. Not only the RF domain, but truly the microwave domain. I frequently get asked how I made the transition from power to microwave. The answer is I jumped in, read everything I could, and made friends with microwave engineers. It takes effort, but it is doable. Simulators like Keysight’s Pathwave ADS recognize this and with their various simulators try to make the process transparent. Workshops and webinars help too. I won’t kid you; this takes effort. The engineers who successfully make the transition will thrive and those that don’t may find themselves irrelevant before too long.
KLC: From a test equipment point of view, let’s say a power supply designer’s equipment is all at least ten years old. Is this okay? What can they keep? What must they discard? What must they do to keep up with the evolution of our industry?
SMS: Not just because of the equipment’s age, I still have a Tektronix 11801B TDR that’s 30 years old. I used it less now because it’s big than because it’s not good enough. I will say that most power engineers are very seriously under-equipped. In this case you will likely get bit by what you didn’t see. I don’t suggest anything less than 2GHz as acceptable today and that bandwidth increases every year, so plan ahead. A bigger issue is probes. Most probes aren’t up to snuff. What sense does it make for the cable to set the limit for your test? See Reference 4.
KLC: A side-effect of the COVID-19 pandemic is that more and more engineers are working remotely—in home labs, for example. The lesson of disease risk in people crowded together is fresh in our minds. Personally, I love this trend toward decentralized work. As a supplier of test equipment, what do you see? Put on your prognosticator hat. Is this remote-work trend a blip, or do you see this as a permanent change?
SMS: Interestingly, we expected our sales would suffer due to the pandemic, but we actually had a significant increase. Mostly, this is due to engineers who are now working from home and need a basic lab setup. Engineers are split on whether they love or hate working from home. Some are self-disciplined and some aren’t. Some like solitude and some don’t. Overwhelmingly, I think engineers love the freedom the new environment allows—they can spend more time with their family during the day and work at night when the kids are in bed. There is a tremendous flexibility in working from home or remotely. My guess is that this isn’t a blip and engineers will work remotely not all of the time, but much of the time.
KLC: Thank you, Steve, for taking time to chat with me. I think engineers will find your perspective informative and interesting.
Author, educator and engineer Steve Sandler is the managing director of Picotest, www.Picotest.com
Reference 1: The Inductive Nature of Voltage Control Loops, Steve Sandler, EDN, February 5, 2015.
Reference 2: Relating SI & PI for High-Speed Digital Boards: FPGA DDR4 Case Study, DesignCon 2020, Steve Sandler, Heidi Barnes and Jack Carrel. Paper available by request.
Reference 3: Just How Fast is GaN Fast?, Steve Sandler, Signal Integrity Journal, March 12, 2020.
Reference 4: Measuring a Scope Probe Requires Two Oscilloscope Channels and a Very Flat Signal Source, Steve Sandler, Signal Integrity Journal, June 25, 2019.