A Talk About Power Integrity and PCB Impacts with Steve Sandler and Robert Feranec
This is a GREAT webinar discussing what is important when designing boards and power supplies with high current loads.
Discussion topics include: Current state of the art in sub 1V/Power Rail Amp Loading Why plane inductance is the biggest challenge given excess inductance control Minimizing the plane and other sources of inductance Thinner dielectric for even lower inductance Decoupling the ASIC Minimizing the inductance Thinner dielectric for even lower inductance How do we carry the current efficiently Stability - Both input and output (control loops) What VRMs can supply this kind of current? Is GaN the answer? Testing gets really tough – So what do I do?