By Steve Sandler
Abstract:
Power integrity and system engineers have the task of designing, optimizing, and assessing the power distribution network impedance. EM simulators are used to model these networks to optimize the decoupling capacitors and to perform worst case assessments, using simulated dynamic chip currents and applying worst case tolerances. Once the hardware is constructed, measurements are performed for correlation, so that the model can be validated. Many engineers struggle to achieve reasonable part model and circuit model correlation. This paper explores two prevalent reasons for this shortfall and provides a methodology for performing accurate capacitor measurements to achieve these correlations. Published in: 2022 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI) Date of Conference: 01-05 August 2022 Date Added to IEEE Xplore: 26 September 2022 ISBN Information: Electronic ISBN:978-1-6654-0929-2 USB ISBN:978-1-6654-0928-5 Print on Demand(PoD) ISBN:978-1-6654-0930-8 INSPEC Accession Number: 22183994 DOI: 10.1109/EMCSI39492.2022.9889500 Publisher: IEEE Conference Location: Spokane, WA, USA
I. Introduction Decoupling capacitors are placed on the printed circuit board to counteract excess inductance from the voltage regulator, bulk capacitors, and power planes. The decoupling capacitors, placed much closer to the ASIC reduce the inductance, thereby containing the voltage excursions caused by the high-speed dynamic current of the ASIC or integrated circuit [1]. Presenting the correct capacitance to counteract the inductance results in the flattest impedance and the smallest step load excursions. Fig. 1.
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