Clock Power Optimization Depends On Jitter Control

Clock-jitter performance has become a top priority among clock, analog-to-digital controller (ADC), and power-supply manufacturers. Why? Simply, it interferes with the performance of digital circuits, particularly high-speed ADCs. High-speed clocks can be quite sensitive to input power “cleanliness,” though quantifying the relationship takes some effort.

New lines of regulators (predominantly low-dropout regulators, or LDOs) coming from voltage-regulator manufacturers promise higher power-supply rejection ratio (PSRR) specifically for powering precision clocks and sensitive circuits. In addition, recent articles reveal that the performance of the clock and subsequent high-speed ADCs can be quite acceptable when replacing the linear regulator with a switching regulator.1


Figure 1 shows a test setup for measuring clock phase noise and jitter. The clock is connected to the Picotest J2180A preamp to connect the high-impedance clock to the 50-? spectrum analyzer. The J2130A dc bias injector eliminates any potential dc voltage at the spectrum analyzer, which could overload the spectrum analyzer ADC.

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