Hi,
The impedance of a PDN is not some kind of a monolithic thing. It varies based on where it is measured or simulated. For most of the FPGAs and other high performance load chips, I think there are three important locations where we should check the PDN impedance - near the VRM, near the load, and on the die inside the load device.
(1) I feel that for the last one - "on the die", it is mostly simulated than measured (with the help of S-parameters) - unless we are working for IC vendor company with specialized IC at our disposal. Am I correct?
(2) Dr. Eric Bogatin, in one of his webinars, measured and demonstrated that the noise signature outside the chip and inside the chip at the the die are very different due to the low pass filter created by package inductance and die capacitance. Does this mean that the simulation of PDN impedance as seen at the die is equally important as the measurement of the PDN impedance at the board?
(3) When FPGA vendors provide operating conditions like 1V +/- 30 mV, are they talking about at the pins or at the die?
Thanks,
Binayak
1. Thanks for the great comment! I have a friend Raj Nair who is an ON-DIE PI expert. On-die is also not monolithic and also depends on where you measure. The die has a PDN just like the board, only smaller. Yes, few have the luxury of measuring on-die, but the semiconductor guys, in general, can measure on die and companies like Cascade make specialized probes for this purpose.
2. Yes, of course! But few of us have that luxury. Semiconductor companies often consider the package/die to be "secret sauce" and so are reluctant to share it. In our Picotest/Keysight/XILINX DesignCon sessions we have been exploring this together and, in particular, see our DesignCon 2021 paper. We showed this interface and how the board impedance interacts at the die. We also explored the hand-off. In this case the hand-off is at a low frequency (<10MHz) thanks to the package filtering, and it would be good to know this. The PCB impedance STILL impacts the die, even with all this filtering.
3. This is a particularly ambiguous point and many semiconductor companies won't provide a direct response. I think, and in our work state this clearly, that we assume this to be at the balls, since we generally don't have access or knowledge beyond that point. In my opinion, this will evolve as it becomes more problematic and at least simplified models of the package/die will become more accessible.