Yes, the pins are quite sharp, partly to get through coating, but also because we have few choices in this size. I think the vias are probable a good option, and we are also looking at selective hard gold plating as an option. We'd really love hearing thoughts from the community as well.

I can't see settings, like the signal injection amplitude, or calibration. The measurements in the app note you linked were not measured by us, and you can see in some of the measurements there was significant overdrive. What I can do, is I can measure a board here using a FRA and see if these are inline with your measurements. I can see what is important to take away from your measurements and that is that the ceramic capacitor has much worse stability than the aluminum or combined capacitors and also that the load current impacts the stability as well. If you write to me at steve@picotest.com, I can provide you with my measurement results as soon as I do the measurements .

I would need a little more information. What is the current range you want to generate? The J2111A may need separate bias to achieve very low current. Often photodiode are used for this when the current is small. If you write to me at steve@picotest.com, I'm happy to help.

That's a really good question, Ryan. Thanks for asking it! You can use the calibration to remove the error, but the result will be very poor. Say the ground loop resistance is 20mOhms. So when you calibrate, the short Calibration subtracts 20mOhms from the measurement. The sensitivity to errors (like say contact resistance) is one. A 1 mOhm change in contact resistance, for example, shows up as a 1 mOhm error. Adding the coaxial isolator divides the 20mOhms by the CMRR of the isolator prior to the calibration and the sensitivity becomes 1/CMRR. If CMRR IS 100dB, you can see the error from the 1mOhm contact resistance change is now 100nOhms. Huge difference. So the answer is that we become much less sensitive to the changes in path resistance using the coaxial transformer.

1. Thanks for the great comment! I have a friend Raj Nair who is an ON-DIE PI expert. On-die is also not monolithic and also depends on where you measure. The die has a PDN just like the board, only smaller. Yes, few have the luxury of measuring on-die, but the semiconductor guys, in general, can measure on die and companies like Cascade make specialized probes for this purpose. 2. Yes, of course! But few of us have that luxury. Semiconductor companies often consider the package/die to be "secret sauce" and so are reluctant to share it. In our Picotest/Keysight/XILINX DesignCon sessions we have been exploring this together and, in particular, see our DesignCon 2021 paper. We showed this interface and how the board impedance interacts at the die. We also explored the hand-off. In this case the hand-off is at a low frequency (<10MHz) thanks to the package filtering, and it would be good to know this. The PCB impedance STILL impacts the die, even with all this filtering. 3. This is a particularly ambiguous point and many semiconductor companies won't provide a direct response. I think, and in our work state this clearly, that we assume this to be at the balls, since we generally don't have access or knowledge beyond that point. In my opinion, this will evolve as it becomes more problematic and at least simplified models of the package/die will become more accessible.

You bet, I am sure many others will benefit from your questions ;)

Excellent questions! 1) If you want to measure the capacitor, say for modeling purposes, remove the cap for the measurement. If you measure PDN impedance on a capacitor, the results will be distorted, but probably fine for measuring the VRM impedance or NISM If you want to measure the plane impedance, a pair of pads side by side works. There will still be some coupling, which is why Istvan Novak recommends 2-sided measurement (others have papers on single sided measurement). The most important thing is to measure and simulate at the same locations and the same way. Eventually the measurement will run out of fidelity, while the simulation still has plenty of fidelity to offer . Our goal is to get confidence in the model so that we can trust the simulator when we get tot hat point. I did cover this topic in my EDICON online presentation a week or so ago. You should be able to watch that on-demand now and I even showed the 4-pad measuremenrt.

Thanks for writing! Glad you liked the paper, and thanks for your interesting insight and question. There is a line between power electronic and power integrity, and I've been fighting for years to remove it. The power supply guy generally simulates using some type of free simulator, with a vendor model. These, independently are bad choices and together they are next level bad. I chose ADS, because it supports analog, digital, RF and uWave. PEPro, PIPro, and SIPro greatly simplify the EM process, using 2 or 2.5D. Modeling is expensive and to create one using a simulator that can't be used at the system level is a waste of time and money. These vendor models also tend to be quite poor. Today we often see divergence between SPICE and EM as low as 100kHz or so, so EM is essential, particularly in performance systems. I've given webinars, videos and even IEEE presentations on VRM Modeling. These models are parameterized, so easy to create, reusable and extremely accurate to 1/6th switching frequency. If you can't find them, email me at Steve@picotest.com and I'll provide some links. Once this is added, optimizers, like the decoupling optimizer help manage the PDN, package and die. See our DesignCon paper from last year (again Heidi, Jack and I) and yes, we have another one together later this month at DesignCon, tough I won't be present for it.

yes, please email me at Steve@picotest.com

I don't know how much higher you want to go in current, but I believe you can probably push it to 450V. It would exceed our derating guidelines, but the capacitors are rated for 500V. At some point you'll thermally kill it, but if you wanted to go to 25Amp I would say maybe, especially if you don't run it there continuously. As a controlled experiment, I think it would be ok...

We do have some application info and also did some videos and webinars I can send, but they won't be all that helpful for you. We typically show step down regulator inductors, which are much lower value, since we don't get many requests for higher inductances. At high inductance, you will run into the noise limitations of the internal hall sensor as you have seen. The voltage drop of the J2121A is only 700mV, so realistically, you can't modulate more than about 500mVpk, that's why increasing the signal level doesn't really help at some point. I think you have 4 options to improve your measurements. Try reducing the RBW from 100 Hz to 10Hz Try trace averaging, which I admit, I haven't used myself Use an external current probe. That will be lower noise than the internal hall sensor Use a current sense resistor This is a great application, so we'll help as much as you need and maybe end up with an app note for PFC inductors in the end. Can you send us an inductor we can try to measure here? What is the bias current?

Small signal is really defined by the limits of the instrument. While your 10% is reasonable, you could probably use much smaller signals than that. The J2112A is much harder to keep stable, but has a larger current. The input voltage to the instrument depends on the instrument and they are not often well documented. I did just have a $6,000 repair on one of my scopes due to damaging the front end. The Bode 100 is pretty robust, but not all instruments are. A simple trick is to power up with the scope in High Z. The DC block will charge through the scope 1MOhm input impedance. After a few seconds it will be fully charged and you can safely switch to 50 Ohms.

There are some eloads that can be modulated, though I don't really care for them. We do hope to make a lower voltage current injector in the future. We have modified the J2111A for a few customers to go down to 0.7V, but that involves removing the steering network, so you lose the negative power supply support.

We have two methods that will work for you. Here is an app note for the J2121A and I also did a presentation at PSMA2020. You can find the video presentation here https://www.dropbox.com/s/0485cltxclli3ws/PSMA%202020.mp4?dl=0

Hi Nicholas, This was my PhD thesis, which I gave up since I wouldn't publish this derivation. It's one of our premier products, so we won't be publishing it any time soon. It is based on Nichols and includes the maximal response, so it is actually an assessment of stability margin, mapped to 2nd order Bode. It isn't an approximation, it's an exact solution. We did make it available for most VNA's, though, so it is very accessible, just not the derivation or the final equation.

;)

Essentially. A VRM is a sampled data systems and so Nyquist holds that the bandwidth must be less than half the sample rate (switching frequency). In reality I would limit to less than 1/6 the switching frequency.

You bet ;)

Exactly. The error is Rshield divided by CMRR. So when I did the 100uOhm paper I had to both reduce Rshield and also improve CMRR (that's why J2102B is now a "B" and not an "A" ;) ) Of course from this it is also obvious that shorter cables are more better. AND since the 2 shields are in parallel, making one really short helps a lot. That's why you often see components mounted to 1 port of the Bode 100 using an adapter and not a cable ;) Once you get to, and below, 1mOhm everything starts to matter. There are many other benefits of PDN cable too (bandwidth, temperature range, flexibility and shield attenuation). I did show the comparisons in the class, so you should have seen the shield attenuation exercises.

Precisely! No, I get excited about it too ;) Rest assured this took some work to get through. It wasn't obvious to me at first. Once you understand this, you also understand why we designed our own coaxial cable... Our PI goals are very different than SI goals. We care mostly about the shield properties and SI cares mostly about the center conductor properties.