Hi, The impedance of a PDN is not some kind of a monolithic thing. It varies based on where it is measured or simulated. For most of the FPGAs and other high performance load chips, I think there are three important locations where we should check the PDN impedance - near the VRM, near the load, and on the die inside the load device. (1) I feel that for the last one - "on the die", it is mostly simulated than measured (with the help of S-parameters) - unless we are working for IC vendor company with specialized IC at our disposal. Am I correct? (2) Dr. Eric Bogatin, in one of his webinars, measured and demonstrated that the noise signature outside the chip and inside the chip at the the die are very different due to the low pass filter created by package inductance and die capacitance. Does this mean that the simulation of PDN impedance as seen at the die is equally important as the measurement of the PDN impedance at the board? (3) When FPGA vendors provide operating conditions like 1V +/- 30 mV, are they talking about at the pins or at the die? Thanks, Binayak

Hi Steve, One of the attractive aspects of a 2-port probe is the browser type functionality to measure PDN impedance of any board. In lecture "2-Port Impedance Measurement Part-2", you measure the PDN impedance by putting the 2-port 4-point (Kelvin) across two capacitor pads. This means either the capacitors were removed, or the pads were added extra during design time. (1) Can we measure the PDN impedance without removing the decoupling capacitors, since we may not have the luxury to remove them. We will be measuring the PDN impedance or capacitor impedances? How much error does measuring across capacitors create instead of just the pads? (2) For the 4-point probe, we need two capacitor pads side-by-side, correct? Thanks, Binayak