I need to measure the Zpdn of a system, which is currently in the prototype stage. The load will be an SoC, which we don't have yet, so this system will have a custom prototype BGA substrate.
Among other things, I'm prototyping the VRM which can source >100A. I want to measure its impedance across its operating range, so I need to create an equivalent load.
For transients, a LoadSlammer should do the trick. For steady-state Zpdn measurements, I need a DC load. An nice solution would be to synchronise a BODE100 to LoadSlammer pulses, but AFAIK that's not possible (and the durations of the pulses may be too short).
At such high currents, I can't use wires and external electronic loads, due to the DC drops and inductance.
Heat will obviously be an issue, so power resistors in heatsinks look like an option (mounted on the PCB and switched by FETs). Placement and current-share then becomes an issue, and it's clear that these devices aren't designed to minimise parasitic L and C.
I'm wondering if it would be better to build a load on the BGA substrate using FETs? I'm a novice in this area - is there an off-the-shelf, small-footprint, low-risk way to do this, which makes heat-removal easy? Or is there a better way, which I'm missing?
Thanks in advance.
Correct. The slew rate is a function of the interconnect, but we are measuring about 200ps (yeah with a "P") for the 2A and about 500ps for the 20A. The plan is to use these in a large array for in-socket emulation. Slew rate would then be controlled by stepping of incremental devices. So turn on one device, wait, turn on another device, wait, turn on another device....
Closing a control loop would be tricky, since GaN isn't all that stable and really wouldn't like interconnect wires. We thought about it in a probe, and it might actually be possible with a bandwidth below about 100MHz. Then it is in a dissipative mode and cooling the probe is difficult, though we are looking at water cooling the probes.
You might also expect to see a beefed up J2112A in a probe. J2112A is also limited mostly by the interconnects. Again for actual loading (as opposed to impulse) expect water cooling...
Very interesting, and very impressive.
So there's no defined slew-rate? Just a switch-on time of (guessing) <1ns? Slew-rate specification is actually a problem for us. When a fast accelerator-core changes state and starts pulling current, it can happen in 1 clock cycle.
I'm going to talk to the rest of my team about this - I'll be in touch.
Thanks for this. Is the PicoSlammer available as a product yet?
Brendan, kudos to you for starting early and thinking about this process. There are really a few separate issues here:
1) DC loading. The importance here is that the impedance of the load (including interconnects) is substantially greater than the VRM impedance. Whether you use resistors or an Eload this still holds true. In my POWER INTEGRITY book, I talked about the capacitive nature of Eloads, the interactions of control loops, etc. So if you measure your Eload and you can maintain adequate separation of the load and VRM impedances (10-20 dB separation, depending on the the angles), you're good.
Resistors work, but you don't have so much resolution. Of course in socket loads (like VRTestTool) are designed for this. If you want to use resistors, you might find old carbon pile adjustable loads on Ebay or we could arrange these for you https://www.contrex.si/en/product-category/variable-resistors/
2) Impedance measurement. The impedance measurement is independent of the load and interconnects, and is typically based on the 2-port shunt through, which the Bode 100 does well. The Bode 100 does have a full automation interface if you feel like programming measurement intervals you could.
3) Transient Step Load testing is a large signal test, not a measure of stability, so different than the impedance. Load Slammer works if it's fast enough (it likely is for the VRM and not for the PDN). The limitation is the power dissipation, so the LoadSlammer wont allow you to dwell at a load current. This means you would use a DC load for the static part and a LoadSlammer or similar for the transient generator. If you use a Picoslammer, that's similar, and in a probe, but fast enough to test the PDN as well (500ps for a 20Amp step and scalable to more than 1kAmp).
As you mentioned, you could build a load in a BGA pattern (and use a CPU water cooler), much like the VRTestTool. Our Picoslammer is also scalable for this solution, just much faster than Si Mosfets could provide. This path would take both time and money, so the question would be whether you could scale the solution to other projects or would it be "one and done". Only you (and your team) can determine if this amortization across programs makes economic sense.
We can certainly assist you with creating or obtaining a validated solution in any one of these routes, so feel free to reach out to us directly to discuss your specific needs. You can contact me directly at email@example.com.