Hi,
I read the excellent DesignCon paper ('Power Integrity for 32 Gb/s SERDES Transceivers', by PICOTEST, Xilinx & Keysight), referenced in Lesson 1.
In this paper, the advantage of raising the switching frequency of a DCDC is explored. I've had recent experience of choosing the BW of a DCDC converter's control-loop, which begs the question: 'How can we confidently simulate, to choose the highest practical BW of a DCDC, which will be well-behaved in a given PCB layout?'
I would like to simulate the whole post-layout system: PSU, PDN and PCB, but sims of PCB parasitics are generally seen to be in a different world to sims of PSUs. When the frequencies of interest really are distinct this is fine, but I believe the line is being blurred.
I can import a synthesised SPICE model of a [PCB+Package+die] Sigrity extraction into an LTspice time-domain sim with a power-supply, but it's hard to find examples of such whole-system sims, which makes me wary of doing this.
Another reason I'd like to run whole-system sims is that modern core-rail transients caused by state-changes in accelerators can be very harsh (tens of amps in a few ns). These can have low repetition rates that fall within DCDC converter loop-BWs. It would be great to simulate everything in one large SPICE sim: DCDC, Cbulk, PCB, PDN, package, package-PDN, die, with the step-loads applied across the Cdie terminals. This would allow inspection of voltage deviation where it matters: at the die, which would also reveal resonances within the package.
As my employer builds its own SoCs, I believe I should be able to achieve this.
My question is quite general - all opinions and advice are welcome:
- Why is this not done more widely? Are sims like this just too complex to be done with confidence?
- Full 3D extractions of entire boards into many GHz aren't practical, so what can be done to constrain the required complexity of the extraction?
- There are many way in which this could go wrong. What can be done to make this work reliably? In order to build confidence in such sims, what steps should be taken in building prototypes, and making measurements & models?
Best regards,
- Brendan
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Thanks for writing! Glad you liked the paper, and thanks for your interesting insight and question.
There is a line between power electronic and power integrity, and I've been fighting for years to remove it.
The power supply guy generally simulates using some type of free simulator, with a vendor model. These, independently are bad choices and together they are next level bad.
I chose ADS, because it supports analog, digital, RF and uWave. PEPro, PIPro, and SIPro greatly simplify the EM process, using 2 or 2.5D.
Modeling is expensive and to create one using a simulator that can't be used at the system level is a waste of time and money. These vendor models also tend to be quite poor.
Today we often see divergence between SPICE and EM as low as 100kHz or so, so EM is essential, particularly in performance systems.
I've given webinars, videos and even IEEE presentations on VRM Modeling. These models are parameterized, so easy to create, reusable and extremely accurate to 1/6th switching frequency.
If you can't find them, email me at Steve@picotest.com and I'll provide some links.
Once this is added, optimizers, like the decoupling optimizer help manage the PDN, package and die.
See our DesignCon paper from last year (again Heidi, Jack and I) and yes, we have another one together later this month at DesignCon, tough I won't be present for it.
Great question Brandon, as you know I'm an advocate of end to end simulation. I chose ADS, since at Supports that, including the analog parts. Look up my papers om Measurement Based Modeling and/or my Keysight How To Videos (primarily for VRM). Thise will show you how we do these simulations and also the mathematics behind the switching frequency.
If you can't find the papers, let me know and I'll point you...