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Your one-stop resource for all things DesignCon 2023

DesignCon 2023: News

PICOTEST PRODUCTS FEATURED IN EXPO BOOTHS

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P2124A High Speed Line Modulator (The World's First PSNR/PSMR/PSRR Probe!): Tektronix 727 (during book signing on Thursday; details below), Molex 739

TDR Bundle - J2154A PerfectPulse® Differential TDR/P2105A 1-Port TDR Probe:

Siglent 1254

Injectors:

Keysight Technologies 1039, Rohde & Schwarz 1049

P2102A 2-Port Probe:

Keysight Technologies 1039, Rohde & Schwarz 1049, PacketMicro 1255

Coming Soon: Water-Cooled Probe Press Release

TUTORIAL – MEASURING PSNR/PSRR/PSMR TO MEET QSFP/OSFP HIGH-SPEED REQUIREMENTS

Tuesday, January 31 • 9:00 AM - 11:30 AM Pacific Time (US & Canada); Tijuana

Location: Ballroom E

Featuring Picotest's P2124A - the world's first water-cooled probe!

Speakers: Steve Sandler, Picotest, Pavel Zivny, Tektronix, Bob Tarasewicz, Molex, Tony Ambrose, Tektronix

Description:

High-speed technology continues to evolve to ever higher frequencies, placing pressure on high-speed in­terconnects. At much lower frequencies, the impacts are seen in PI. PI challenges are generally more related to the low impedance of the circuitry, while signal integrity (SI) challenges are more related to the higher frequen­cies. Both the PI and the SI challenges must be met to achieve the system-level performance. This includes the testing aspects, as well as general operation. As a re­sult, both SI and PI have noise and interconnect challenges, though the challenges are different. New, higher speed devices such as the Quad Small Form-factor Pluggable (QSFP) Double Density 8× and QSFP 4× pluggable transceivers require testing to much higher bandwidths.


In this tutorial, we focus on power supply rejection ratio (PSRR), power supply modulation ratio (PSMR), and power supply noise rejection (PSNR) measurements, which are all measures of how pow­er rail noise appears at the output of voltage regulators, RF amplifiers, and digital channel jitter. PSNR on 400/800G transceivers will be a focus. The test solution using the P2124A, the first water cooled testing probe for PSNR noise immunity applications is explored.


The impact of power supply noise on high performance systems is well established, and as a result, many applications now require power supply sensitivity testing to assure robust designs. There are numerous obstacles to overcome, beginning with nomenclature. Different applications use various naming conventions for power supply sensitivity. In power electronics, we refer to this as PSRR or Power Supply Ripple Rejection, while in RF we refer to this as PSMR or Power Supply Modulation Ratio, and in high-speed transceivers we refer to this as PSNR or Power Supply Noise Rejection. The most recent QSFP-DD optical transceiver specification, QSFP-DD-Hardware-Rev6.3, for example, requires noise to be injected onto the power supply input over a frequency range of 40Hz-10MHz. This is challenging at the very least, leaving engineers to not only perform the test, but to develop the methods and equipment required. In this session, we present the requirements, measurement challenges, and proposed solution, including the test setup, for performing these difficult tests.


Live demonstrations of PSRR testing of (power supplies) using an MS06 oscilloscope, PSMR using Signal View software, and PSNR using a 112Gb/s PAM-4 – PCIe application will be presented.


Type: Tutorial

Pass Type: All Access Pass

Theme: High-speed Communications, Data Centers

TRACKS:

Coming Soon: Download Support Files

VRM MODELING AND STABILITY ANALYSIS FOR POWER INTEGRITY ENGINEERS

Wednesday, February 1 • 9:00 AM - 9:45 AM Pacific Time (US & Canada); Tijuana
Location: Ballroom F

Speakers: Heidi Barnes, Keysight, Steve Sandler,  Picotest, Christian Yots, Texas Instruments, Benjamin Dannan, Northrop Grumman

Description:

In the world of power electronics, the focus is on the power supply and the load is a simple resistor. In the world of power integrity, the focus is on the decoupling capacitors required for the digital load and the power supply is a simple resistor in series with an inductor. In the real world neither assumption solves the problem of simulating the power delivery ecosystem with switching power supply control loops, gigabit switching digital loads, and a PCB network of filtering and decoupling components. The challenge is, how to simulate the Power Integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results?

The solution presented here uses control loop theory state equations to create a behavioral model of an SMPS that allows for fast simulation. This Sandler State Space Average Model previously published [1] has the fidelity to include the dynamic control loop behavior for stability assessment, large signal and small signal noise ripple, and power supply rejection ratio. The model also works with the Non-Invasive Stability Measurement method to assess control loop phase margin from simple output impedance data.

Type: Technical Session

Pass Type: 2-Day Pass, All Access Pass

Theme: Automotive, Data Centers

TRACKS:

Coming Soon: Download Support Files

A NEW POWER INTEGRITY REQUIREMENT TO SUPPLEMENT TARGET IMPEDANCE: QUANTIFYING PDN IMPEDANCE FLATNESS FROM SANDLER NISM

Wednesday, February 1 • 11:15 AM - 12:00 PM Pacific Time (US & Canada); Tijuana

Location: Ballroom G

Speakers: Scott Witcher, AEi Systems, Steve Sandler, Picotest

Description:

Target impedance is the most common power distribution network (PDN) design requirement used in industry today, but it is fundamentally limited because it does not account for PDN voltage responses to different load current waveform shapes, and can only predict worst-case voltage excursions in the specific case of a flat PDN impedance profile. Since no impedance path is perfectly flat, and PDNs inevitably contain one or more resonances that can generate worst-case voltage excursions, it is critical to quantify whether PDN impedance profiles are "flat enough." This paper presents a methodology to quantify PDN impedance flatness using quality factor (Q), group delay, and Sandler Non-Invasive Stability Measurement (NISM). It also proposes a PDN impedance flatness requirement to supplement target impedance requirements.

Type: Technical Session

Pass Type: 2-Day Pass, All Access Pass

Theme: High-speed Communications, Consumer Electronics

TRACKS:

Coming Soon: Download Support Files

BOOK SIGNING AND AUTHOR MEET AND GREET

Wednesday, February 1 • 4:15 PM - 5:00 PM Pacific Time (US & Canada); Tijuana
Location: Samtec Booth #939

Authors: Istvan NovakSteve KrooswykEric Bogatin, Pete Pupalaikis, Steve Sandler, and John Riley

Attendees will be invited to stop by and chat with authors and bring their books for signing if they wish. Some books will be available in the booth for signing. Attendees who want them can scan their badge (Samtec will indicate they want the raffle), and then Wednesday night or early Thursday morning the winners will get an email inviting them back to the booth to pick up their signed book. If someone will not be attending that day, Samtec will work with them to get them their book. Steve Sandler will be signing copies of “Power Integrity Using ADS.”

PANEL – WHAT USERS NEED FROM POWER INTEGRITY SIMULATORS

Wednesday, February 1 • 4:00 PM - 5:15 PM Pacific Time (US & Canada); Tijuana
Location: Ballroom F

Speakers: Istvan Novak, Samtec, Peter Pupalaikis, Nubis Communications, Eric Bogatin, University of Colorado, Boulder, Ethan Koether, Amazon Project Kuiper, Steve Sandler, Picotest

Description:

Power distribution keeps getting more and more demanding in a lot of electronic designs and the pre- and post-layout PI simulations are becoming an integral part of the design and validation processes. This panel brings together PI tool users from various OEMs with decades of design experience so that they can summarize and discuss the state of the PI simulation tools the way how they have experienced it and lay out the user needs for additional features and capabilities. A follow-up panel will be devoted to the emerging approaches and solutions offered by CAD companies.

Type: Panel Discussion

Pass Type: 2-Day Pass, All Access Pass, Expo Pass

TRACKS:

Coming Soon: Download Support Files

BOOK SIGNING WITH STEVE SANDLER

Thursday, February 2 • 11:00 AM - 11:45 AM Pacific Time (US & Canada); Tijuana
Location: Tektronix Booth #727

CHIPHEADS, HANDS-ON PDN IMPEDANCE & CALIBRATION BASICS

Thursday, February 2 • 12:15 PM - 1:00 PM Pacific Time (US & Canada); Tijuana

Location: Chiphead Theater

Speakers: Heidi Barnes, Keysight, Steve Sandler, Picotest, Benjamin Dannan, Northrop Grumman

Description:

You have probably heard of calibration, de-embedding, and fixture removal for network analyzer measurements, but do you know how to do it for a 2-port shunt low impedance measurement? Impedance measurements are a must have skill for Power Integrity engineers. The measurements provide models for Capacitors, Resistors, and Inductors that work in both time and frequency domain simulations. Impedance measurements are also critical for verifying the performance stability of a power delivery network (PDN).

In this session you'll learn the difference between these terms. You'll learn, with demonstrations, how to remove the impact of fixturing using calibration and de-embedding steps. The process works for both connectorized devices, or with PCB browser probes to provide accurate measurements that are compatible with your PCB EM simulator.


Type: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Expo Pass

TRACKS:

Coming Soon: Download Support Files

RELEVANT APPLICATION NOTES

POWER INTEGRITY TESTING REQUIREMENTS INTRODUCE EXTREME INTERCONNECT MEASURES

Steve Sandler, Picotest, SI Journal, January 24, 2023

"Power Integrity (PI) engineers are familiar with the ground shield effect in the 2-port shunt through measurement. If not, there are many papers, articles, and videos on the subject. PI engineers are less knowledgeable about the impacts on other power related measurements. In this article, we focus on power supply rejection ratio (PSRR), power supply modulation ratio (PSMR), and power supply noise rejection (PSNR) measurements, which are all measures of how power rail noise appears at the output of voltage regulators, RF amplifiers, and digital channel jitter..."

SMALL SIGNAL MODELS, SMALL SIGNAL PROBLEMS

Will McCaffrey, Northrop Grumman, SI Journal, November 15, 2022

"The Voltage Regulator Modules (VRMs) are a vital part of any hardware design and critical to system-level power integrity analysis. When available, VRM models provided by the vendors offer a reasonable starting point for a power integrity design analysis, assuming the model properly represents the output impedance. However, these should not be used for design sign-off. The resistor-inductor (R-L) model is typically the most common SPICE representation for the ideal VRM small-signal passive model..." Ideal VRM models in SPICE can sometimes provide reasonable first-order approximations for circuit behavior

STABILITY AND PERFORMANCE IMPROVEMENT WITH FEEDBACK IN VRM TRANSCONDUCTANCE ERROR AMPLIFIERS - A CASE STUDY USING THE SANDLER STATE SPACE AVERAGE VRM MODEL

Benjamin Dannan, Northrop Grumman, EDICON Online 2022

"The voltage regulator module (VRM) is the foundation of power integrity. Due to their wide bandwidth and low cost, most newer VRM controllers employ transconductance feedback amplifiers, with the VRM manufacturers recommending a shunt compensation for the error amplifier design. However, most VRM designers and power integrity engineers may not be aware that they have another choice to improve the sensitivity and performance of their VRM design. The better performance of a current mode VRM with series compensation for the error amplifier is clearly demonstrated with simulations using the Sandler state-space average VRM model..."

HOW TO TEST PSRR, PSNR AND PSMR FOR SENSITIVE APPLICATIONS, INCLUDING OPTICAL TRANSCEIVERS

Steve Sandler, Picotest, EDICON Online 2022

"The impact of power supply noise on high performance systems is well established, and as a result, many applications now require power supply sensitivity testing to assure robust designs.  There are numerous obstacles to overcome, beginning with nomenclature.  Different applications use different naming conventions for power supply sensitivity.  In power electronics, we refer to this as PSRR or Power Supply Ripple Rejection, while in RF we refer to this as PSMR or Power Supply Modulation Ratio, and in high-speed transceivers we refer to this as PSNR or Power Supply Noise Rejection..."

DesignCon 2023: List
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FIND ME AT DESIGNCON

Look for Picotest and ask for a free probe measurement keychain board!

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